The present invention generally relates to production test requirements for testing programmable impedance drivers such as the BZIO buffers contained in RapidChip and ASIC devices.
The problem faced in the manufacturing test environment is that it is a non-ideal situation with respect to the contact resistance that occurs at multiple points between the tester's pin electronics and the actual device-under-test (DUT). These contact resistances are difficult to control at best, and cannot be completely eliminated. As such, they contribute an error component to any resistance measurements that are to be made on the actual DUT. These errors in the measurements result in failing tests during the manufacturing test flow causing product yield issues.
The only existing solutions to the aforementioned problems involve the relaxation of test limits for the DUT, or the elimination of the test altogether. While this can address the manufacturing test problem, it increases the possibility of shipping product that is out of specification. Alternatively, the testing can be done within the specified test limits, and then one is forced to accept any associated yield losses during the manufacturing test process.
As discussed, the disadvantage of the existing solutions as far as changing the test limits is the possibility for shipping product which is out of specification to the customer. If there are no changes made to the test program and the DUT is tested against specified test limits, then the manufacturer will experience yield losses caused by the uncontrollable error components associated with the test process.
FIG. 1 represents the typical circuit for an n-channel device which is to be measured on the DUT, including the error components which are an inherent part of the measurement process. A programmable impedance driver typically consists of several transistor ‘legs’ which can be selectively turned on to provide varying drive strengths. Regardless of the combination of those various transistor legs, the final effective drive strength can be viewed as a lump-sum resistance of the transistors in their ‘ON’ state. This is the value RTransistor shown in FIG. 1. The labels ‘Ground’ and ‘Signal Pad’ refer to the contact points between the ATE pin electronics and the DUT, while ‘RGround’ and ‘RSignalPad’ refer to the contact resistances associated with those connections. These contact resistances are what contribute to the error components of the test measurement, resulting in the inability to accurately test the RTransistor value. The standard approach to measuring the on-resistance of a transistor or transistor network on the ATE is to inject a current at ‘Signal Pad’ and measure the resultant voltage at the pad. The transistor on-resistance is then calculated using Ohm's law, or R=V/I. The problem is that the calculated on-resistance includes the unknown error components associated with ‘RGround’ and ‘RsignalPad’.